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Low Start-Up Current PFC/PWM Controller Combos
Features
* * * * * * * * * * * * * * * * Low start-up current(100A typ.) Low operating current(2.5mA typ.) Low total harmonic distortion, high power factor Pin-compatible upgrade for the ML4800 Average current, continuous, or discontinuous boost leading edge PFC Slew rate enhanced transconductance error amplifier for ultra-fast PFC response Internally synchronized leading edge PFC and trailing edge PWM Reduction of ripple current in the storage capacitor between the PFC and PWM sections PWM configurable for current mode or voltage mode operation Additional folded-back current limit for PWM section 20V BiCMOS process VIN OK guaranteed turn on PWM at 2.25V Vcc OVP Comparator, Low Power Detect Comparator Current-Fed gain modulator for improved noise immunity Brown out control, over-voltage protection, UVLO, soft start, and Reference OK Available in a 16-DIP Package
FAN4800
General Description
The FAN4800 is a controller for power factor corrected, switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with the IEC-1000-3-2 specifications. Intended as a Bi-CMOS version of the industry-standard ML4800, the FAN4800 includes circuits for the implementation of leading edge, average current, boost type power factor correction and a trailing edge, pulse width PWM (Pulse Width Modulator). A gate driver with 1A capabilities minimizes the need for external driver circuits. Low power requirements improve efficiency and reduce component costs. An over voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, at up to 250kHz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. The FAN4800 includes a folded-back current limit for the PWM section to provide a short circuit protection function.
16-DIP
Applications
* * * * * * * * Desktop PC Power Supply Internet Server Power Supply Un-interruptible Power Supply UPS Battery Charger DC Motor Power Supply Monitor Power Supply Telecom System Power Supply Distributed Power
Rev. 1.0.0
(c)2005 Fairchild Semiconductor Corporation
FAN4800
Internal Block Diagram
VEAO VFB
16
IEAO
1
POWER FACTOR CORRECTOR
Vcc 17.9V 0.5V -1V Vcc OVP 2.78V
TRI-FAULT S R
13
Vcc 7.5V REFERENCE VREF
PFC OVP
14
15
2.5V
0.3V 3.5k
Low Power Detector
Q
2 4 3 7
IAC VRMS ISENSE RAMP1
GAIN MODULATOR
PFC OUT PFC ILIMIT
S R Q
3.5k
PFC CMP
12
OSCILLATOR CLK DUTY CYCLE LIMIT
8
RAMP2
350
PWM DUTY
PFC OUT PWM OUT
PWM CMP
0.95V
6
VDC
Vcc
20uA
SS CMP 1.0V
PWM OUT
S Q R
11
5
SS
350
VFB 2.25V VIN OK DC ILIMIT
VREF 9
DC ILIMIT Q S R Vcc
UVLO
GND
10
PULSE WIDTH MODULATOR
2
FAN4800
Pin Configuration
1616 - Pin PDIP
16
IEAO IAC
VEAO
VEAO 16 6
1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8
V FB
15 5 V FB
15
FAN6800 FAN6800 FAN6800 FAN6800
SS
ISENSE
V REF
VREF 14 4 13 3
14
V RMS
Vcc
PFCOUT PWMOUT
VCC CC CC CC
13
PFC OUT
11 1
12 2
12
V DC RAMP1 RAMP 1 RAMP2 RAMP 2
PWM OUT
GND
DC ILIMIT
11
DC ILIMIT
10 10 10 10 9
GND
10 9
Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol IEAO IAC ISENSE VRMS SS VDC RAMP1 (RtCt) PFC gain control reference input Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation Connection point for the PWM soft start capacitor PWM voltage feedback input Oscillator timing node; timing set by RT, CT Description PFC transconductance current error amplifier output
RAMP2 In current mode, this pin functions as the current sense input; in voltage mode, it is the (PWM RAMP) PWM input from the PFC output (feed forward ramp) DC ILIMIT GND PWM OUT PFC OUT VCC VREF VFB VEAO PWM current limit comparator input Ground PWM driver output PFC driver output Positive supply Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output
3
FAN4800
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Parameter VCC IEAO ISENSE Voltage Voltage on Any Other Pin IREF IAC Input Current Peak PFC OUT Current, Source or Sink Peak PWM OUT Current, Source or Sink PFC OUT, PWM OUT Energy per Cycle Junction Temperature Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering,10 sec.) Thermal Resistance(JA) Plastic DIP Min.
-
Max. 20 5.5 0.7 VCC+0.3 10 1 1 1 1.5 150 150 125 260 80
Unit V V V V mA mA A A J C C C C C/W
0 -5 GND-0.3
-
-
-65 -40 -
Electrical Characteristics
Unless otherwise stated, these specifications apply: VCC=15V, RT=52.3K, CT=470pF, TA= -40C to 125C Parameter VOLTAGE ERROR AMPLIFIER Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Sink Current Source Current Open Loop Gain Power Supply Rejection Ratio Vfb gm1 Vref(PFC) Ib(Veao) Veao(H) Veao(L) Isink(V) Isource(V) Gv PSRR1 TA =25C Note1 TA =25C, VFB = 3V VEAO = 6.0V TA =25C, VFB = 1.5V VEAO = 1.5V Note2, Note3 11V < VCC < 16.5V(Note3) Note3 0 50 2.45 -1.0 5.8 30 50 50 70 2.5 -0.05 6.0 0.1 -35 40 60 60 6 90 2.55 0.4 -20 V mho V V V A A dB dB Symbol Test Conditions Min. Typ. Max. Unit
4
FAN4800
Electrical Characteristics (Continued)
Unless otherwise stated, these specifications apply: VCC=+15V, RT=52.3K, CT=470pF, TA= -40C to 125C. Parameter CURRENT ERROR AMPLIFIER Input Voltage Range Transconductance Input Offset Voltage Input Bias Current Output High Voltage Output Low Voltage Sink Current Source Current Open Loop Gain Power Supply Rejection Ratio PFC OVP COMPARATOR Threshold Voltage Hysteresis Threshold Voltage VCC OVP COMPARATOR Threshold Voltage Hysteresis TRI-FAULT DETECT Time to Fault Detect High Fault Detect Low PFC ILIMIT COMPARATOR Threshold Voltage (PFC ILIMIT VTH - Gain Modulator Output) Delay to Output(Note 3) DC ILIMIT COMPARATOR Threshold Voltage Delay to Output(Note 3) VIN OK COMPARATOR Threshold Voltage Hysteresis Vth(OK) HY(OK) 2.10 0.8 1.0 2.45 1.2 V V Vth(DC) Td(pwm_off) 0.95 1.0 250 1.05 V ns Vth(cs) Vth(cs)-Vgm Td(pfc_off) -1.10 5 -1.00 100 250 -0.90 V mV ns Td(F) F(L) VFB=VFault Detect LOW to VFB=Open. 470pF from VFB to GND(Note3) 0.4 2 0.5 4 0.6 ms V Vcc_ovp HY(Vcc_ovp) TA =25C TA =25C 17.5 1.40 17.9 1.5 18.5 1.65 V V Vovp HY(ovp) Vth(lp) TA =25C TA =25C TA =25C 2.70 230 0.15 2.78 0.3 2.9 350 0.4 V mV V Vieao gm2 Voffset Ibeao Ieao(H) Ieao(L) Isink(I) Isource(I) Gi PSRR2 Note3 TA =25C Note3 -1.5 50 -1 4.0 35 60 60 85 4.25 1.0 -65 75 70 75 0.7 100 25 1.2 -35 V mho mV A V V A A dB dB Symbol Test Conditions Min. Typ. Max. Unit
ISENSE = +0.5, IEAO = 4.0V ISENSE = -0.5, IEAO = 1.5V
Note3 11V < VCC <16.5V(Note3)
LOW POWER DETECT COMPARATOR
5
FAN4800
Electrical Characteristics (Continued)
Unless otherwise stated, these specifications apply: VCC=15V, RT=52.3K, CT=470pF, TA= -40C to 125C. Parameter GAIN MODULATOR G1 G2 Gain (Note 2) G3 G4 Band Width Output Voltage = 3.5k * (ISENSE - IOFFSET) OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage PFC Dead Time CT Discharge Current REFERENCE Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Long Term Stability PFC Minimum Duty Cycle Maximum Duty Cycle Output Low Rdson Output Low Voltage Output High Rdson Rise/Fall Time Dmin Dmax Ron(low)1 Ron(low)2 Vol1 Ron(high)1 Ron(high)2 Tr(pfc) VIEAO > 4.0V VIEAO < 1.2V IOUT = -20mA at TA =25C IOUT = -100mA at TA =25C IOUT = -10mA, VCC = 9V at TA =25C (Note3) IOUT = 20mA at TA =25C IOUT = 100mA at TA =25C CL = 1000pF(Note3) 92 95 0.4 15 15 50 0 15 15 0.8 20 20 % % V ns Vref1 Vref1 Vref2 Vref4 Vref2 Vref5 TA =25C, I(VREF) = 1mA 11V < VCC < 16.5V 0mA < I(VREF) < 7mA Line, Load, Temp(Note3) TJ = 125C, 1000hours(Note3) 7.4 7.35 5 7.5 10 10 0.4 7.6 25 20 7.65 25 V mV mV % V mV Fosc1 Fosc1 Fosc2 Fosc2 Vramp Tdead Idis Line, Temp Note3 VRAMP2 = 0V, VRAMP1 = 2.5V TA =25C 11V < VCC < 16.5V 68 66 6.5 2.75 685 1 2 81 84 15 kHz % % kHz V ns mA BW Vo(gm) IAC =100A, VRMS =0, VFB=1V TA =25C IAC =100A, VRMS =1.1V, VFB=1V TA =25C IAC =150A, VRMS =1.8V, VFB=1V TA =25C IAC =300A, VRMS =3.3V, VFB=1V TA =25C IAC =100A(Note3) IAC =250A, VRMS =1.1V, VFB=2V TA =25C 0.70 1.80 0.90 0.25 0.80 0.84 2.00 1.00 0.32 10 1.00 0.95 2.20 1.10 0.40 1.20 MHz V Symbol Test Conditions Min. Typ. Max. Unit
6
FAN4800
Electrical Characteristics (Continued)
Unless otherwise stated, these specifications apply: VCC=+15V, RT=52.3K, CT=470pF, TA= -40C to 125C. Parameter PWM Duty Cycle Range Output Low Rdson Output Low Voltage Output High Rdson Rise/Fall Time PWM Comparator Level Shift SUPPLY Start-up Current Operating Current Under Voltage Lockout Threshold Under Voltage Lockout Hysteresis Ist Iop Vth(start) Vth(hys) VCC = 12V, CL = 0pF 14V, CL = 0pF 12.74 2.80 100 2.5 13 3.0 200 7.0 13.26 3.20 A mA V V D Ron(low)3 Ron(low)4 Vol2 Ron(high)3 Ron(high)4 Tr(pwm) PWM(ls) IOUT = -20mA at TA =25C IOUT = -100mA at TA =25C IOUT = -10mA, VCC = 9V TA =25C IOUT = 20mA at TA =25C IOUT = 100mA at TA =25C CL = 1000pF(Note3) 0-42 0.8 0-47 0.4 15 15 50 0.95 0-49 15 15 0.8 20 20 1.2 % V ns V Symbol Test Conditions Min. Typ. Max. Unit
Note1: Includes all bias currents to other circuits connected to the VFB pin. Note2: Gain = K x 5.375V; K = (ISENSE-IOFFSET) x [ IAC x (VEAO-0.625) ] -1; VEAOMAX = 6V Note3: This parameter, although guaranteed by design, is not 100% production tested.
7
FAN4800
Typical Performance Characteristics
Figure A Voltage Error Amplifier(gmv) Transconductance
Figure B Current Error Amplifier(gmi) Transconductance
Figure C Gain Modulator Transfer Characteristic (K)
Figure D GAIN
K=
I GAINMOD - I OFFSET mV -1 I AC x (6 - 0.625 )
Gain =
I SENSE - I OFFSET I AC
8
FAN4800
Functional Description
The FAN4800 consists of an average current controlled, continuous boost Power Factor Correction (PFC) front end and a synchronized Pulse Width Modulator(PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feed forward from the PFC output bus can be used to improve the PWM's line regulation. In either mode, the PWM stage uses conventional trailing edge duty cycle modulation. This patented leading/trailing edge modulation technique results in a higher usable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC bus capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the FAN4800 runs at the same frequency as the PFC. In addition to power factor correction, a number of protection features are built into the FAN4800. These include soft-start, PFC over voltage protection, peak current limiting, brownout protection, duty cycle limiting, and under voltage lockout (UVLO).
input line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The second condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier, and switching output driver satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. To prevent ripple, which will necessarily appear at the output of boost circuit (typically about 10VAC on a 385VDC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC section to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage Since the boost converter topology in the FAN4800 PFC is the current averaging type, no slope compensation is required.
Power Factor Correction
Power Factor Correction treats a nonlinear load like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak charging effect, which occurs on the input filter capacitor in these supplies, causes brief high amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such supplies present a power factor to the line of less than one(i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the FAN4800 uses a boost mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the
PFC Section
Gain Modulator
Figure 1 shows a block diagram of the PFC section of the FAN4800. The gain modulator is the heart of the PFC, as the circuit block controls the response of the current loop to line voltage waveform and frequency, RMS line voltage, and PFC output voltages. There are three inputs to the gain modulator. These are: 1. A current representing the instantaneous input voltage (amplitude and wave shape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2. A voltage proportional to the long term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The output of the gain modulator is inversely proportional to VRMS2(except at unusually low values of VRMS where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is called K, and is illustrated in the Figure C of the Typical Performance Characteristics. 9
FAN4800
3. The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form of the output of the gain modulator is:
I AC x VEAO I GAINMOD = --------------------------------- x 1V 2 V RMS
amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC , an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator's output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin. Cycle-By-Cycle Current Limiter and Selecting Rs As well as being a part of the current feedback loop, the ISENSE pin is a direct input to the cycle-by-cycle current limiter for the PFC section. If the input voltage at this pin is ever less than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. Rs is the sensing resistor of the PFC boost converter. During the steady state, line input current*Rs equals IGAINMOD*3.5K. Since the maximum output voltage of the gain modulator is IGAINMOD max*3.5K=0.8V during the steady state, Rs*line input current will be limited to below 0.8V as well. Therefore, to choose Rs, we use the following equation:
R = 0.8V x ( V ) ( 2 x Line Input Power )
More precisely, the output current of the gain modulator is given by:
I GAINMOD = K x ( VEAO - 0.625 ) x I AC
where K is in units of V-1 Note that the output current of the gain modulator is limited around 228.47A and the maximum output voltage of the gain modulator is limited to 228.47A* 3.5K = 0.8V. This 0.8V will also determine the maximum input power. However, IGAINMOD cannot be measured directly from ISENSE. ISENSE = IGAINMOD-IOFFSET and IOFFSET can only be measured when VEAO is less than 0.5V and IGAINMOD is 0A. Typical IOFFSET is around 60A. Selecting RAC for IAC pin IAC pin is the input of the gain modulator. IAC is also a current mirror input and it requires current input. Selecting a proper resistor RAC, will provide a good sine wave current derived from the line voltage and also help program the maximum input power and minimum input line voltage. RAC=Vin peak * 7.9K. For example, if the minimum line voltage is 80VAC, the RAC=80*1.414*7.9K=894Kohm. Current Error Amplifier, IEAO The current error amplifier's output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. As stated above, the inverting input of the current error 10
S
INPEAK
For example, if the minimum input voltage is 80VAC, and the maximum input RMS power is 200Watt, RS = (0.8V * 80V * 1.414)/(2*200)=0.226ohm. PFC OVP In the FAN4800, the PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load changes suddenly. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.78V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 280mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.50V. Also, Vcc OVP can serve as a redundant PFC OVP protection. VCC OVP and threshold is 17.9V with 1.5V hysteresis.
FAN4800
VE A O V FB 15
2.5V
16
IE A O
1
P O W ER FAC T O R C O R R EC TO R
13 Vcc
7.5V RE FEREN C E
V cc
0.3V 3.5k Lo w Po w er D e tecto r 17.9V
V cc O VP 2.78V T R I-F AU LT
PF C O VP
V RE F
14
0.5V
S -1V R
Q
2 4 3 7
IAC
VRM S G A IN M O D U LAT O R P FC C M P
P FC O U T PFC ILIMIT S R Q
3.5k
12
ISENSE
RAMP1 O SC ILLA TO R
C LK
Figure 1. PFC Section Block Diagram
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a negative resistor because an increase in the input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: As the reference voltage increases from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter.
The Voltage Loop Gain(S) is given by:
V V V EAO FB OUT = -------------------- x -------------------- x -------------------V V V FB OUT EAO P IN x 2.5V --------------------------------------------------------------------------------------- x GM x Z V C 2 V OUTDC x V xSxC EAO DC
PFC Voltage Loop
There are two major concerns when compensating the voltage loop error amplifier, VEAO: Stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier's open loop crossover frequency should be 1/ 2 that of the line frequency, or 23Hz for 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the FAN4800's voltage error amplifier, VEAO has a specially shaped non-linearity so that under steady state operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbation in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Figure A of the Typical Performance Characteristics. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with conventional linear gain characteristics.
where Zc : Compensation network for the voltage loop GMv: Transconductance of VEAO PIN: Average PFC input power VZOUTDC: PFC boost output voltage; typical designed value is 380V. CDC: PFC boost output capacitor
PFC Current Loop
The compensation of the current amplifier, IEAO, is similar to that of the voltage error amplifier, VEAO, with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. The Current Loop Gain(S) is given by:
V D I ISENSE OFF EAO = ------------------------------- x -------------------- x ------------------------------D OFF I EAO V ISENSE V xR OUTDC S ----------------------------------------- x GM x Z I CI S x L x 2.5V
where ZCI: Compensation network for the current loop GMI: Transconductance of IEAO VOUTDC: PFC boost output voltage; typical designed value is 380V. The equation uses the worst condition to 11
FAN4800
calculate the ZCI Rs: Sensing resistor of the boost converter 2.5V: Amplitude of the PFC leading modulation ramp L: boost inductor A modest degree of gain contouring is applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Figure A of the Typical Performance Characteristics.
Vref
design the pole of ISENSE filter at Fpfc/6, one sixth of the PFC switching frequency. Therefore, the boost inductor can be reduced 6 times without disturbing the stability. Thus the capacitor of the ISENSE Filter, CFILTER, will be around 283nF.
VBIAS RBIAS
Vcc 0.22uF Ceramic 15V Zener
FAN4800
GND
PFC Output VEAO VFB 15
2.5V
Figure 3. External Component Connection to Vcc
16
IEAO
1
Osillator(RAMP1)
The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock:
3.5k
f
OSC
1 = ------------------------------------------------------------t +t RAMP DEADTIME
2 4 3
IAC
VRMS Gain Modulator PFC CMP
3.5k
The dead time of the oscillator is derived from the following equation:
t V REF - 1.00 = C x R x In --------------------------------- RAMP T T V REF - 3.75
ISENSE
Figure 2. Compensation Network Connection for the Voltage and Current Error Amplifiers
at VREF =7.5V and tRAMP = CT * RT* 0.55 The dead time of the oscillator may be determined using:
t DEADTIME 2.75V = ----------------------- x C = 227 x C T T 12.11mA
ISENSE filter, the RC filter between Rs and IENSE: There are two reasons to add a filter at ISENSE pin: 1) Protection: During start up or in-rush current conditions, it will have a large voltage cross, Rs, which is the sensing resistor of the PFC boost converter. It requires the ISENSE filter to attenuate the energy. 2) To reduce L, the Boost Inductor: The ISENSE filter also can reduce the Boost Inductor value since the ISENSE filter behaves like an integrator before ISENSE pin which is the input of the current error amplifier, IEAO. The ISENSE filter is an RC filter. The resistor value of the ISENSE filter is between 100ohm and 50ohm because IOFFSET X Rs can generate an offset voltage of IEAO. Selecting an RFILTER which is equal to 50ohm, will keep the offset of the IEAO less than 5mV. Usually, we 12
The dead time is so small (tRAMP>>tDEAD TIME) that the operating frequency can typically be approximated by:
f OSC 1 = ------------------t RAMP
FAN4800
EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at:
f OSC 1 = 100kHz = ------------------t RAMP
PWM Current Limit
The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. Besides, when the DC ILIMIT triggers the cycle-by-cycle current, it also softly discharges the voltage of soft-start capacitor. It will limit PWM duty cycle mode. Therefore, the power dissipation will be reduced during the dead short condition.
solving for CT * RT yields 1.96 * 10-4. CT is 390pF, and RT is 51.1kohm, selecting standard components values. The dead time of the oscillator adds to the maximum PWM duty cycle (it is an input to the Duty Cycle Limiter). With zero oscillator dead time, the maximum PWM duty cycle is typically 47%. Take care not to make CT too large which could extend the maximum duty cycle beyond 50%. This can be accomplished by using a stable 390pF capacitor for CT.
VIN OK Comparator
The VIN OK Comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.25V. Once this voltage reaches 2.25V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft start begins.
PWM Section
Pulse Width Modulator
The operation of the PWM section of the FAN4800 is straightforward, but there are several points that should be noted. Foremost among these is the inherent synchronization of PWM with the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current mode or voltage mode operation. In current mode applications, the PWM ramp (RAMP2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter's output stage. DC ILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP2 in such applications. For voltage mode operation, and certain specialized applications, RAMP2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feed-forward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input is used for output stage over current protection. No voltage error amplifier is included in the PWM stage of the FAN4800, as this function is generally performed on the output side of the PWM's isolation boundary. To facilitate the design of opto-coupler feedback circuitry, an offset has been built into the PWM's RAMP2 input that allows VDC to command a zero percent duty cycle for input voltages below typical 0.95V.
PWM Control (RAMP2)
When the PWM section is used in current mode, RAMP2 is generally used as the sampling point for a voltage representing the current in the primary of the PWM's output transformer. The voltage is derived either from a current sensing resistor or a current transformer. In voltage mode, RAMP2 is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2), that will have a minimum value of zero volts and a peak value of approximately 5V. In voltage mode operation, feed-forward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage.
13
FAN4800
Soft Start
PWM start-up is controlled by selection of the external capacitor at SS. A current source of 20mA supplies the charging current for the capacitor, and start-up of the PWM begins at 0.95V. Start-up delay can be programmed by the following equation:
C SS =t 20A x --------------DELAY 0.95V
EXAMPLE: To obtain a desired VBIAS voltage of 18V, a VCC of 15V, and the FAN4800 driving a total gate charge of 90nC at 100kHz (e.g. 1 IRF840 MOSFET and 2 IRF820 MOSFET), the gate driver current required is:
I GATEDRIVE = 100kHz x 90nC = 9mA R BIAS BIAS V -V BIAS CC = ------------------------------------I +I CC G 18V - 15V = ------------------------------5mA + 9mA
where Css is the required soft start capacitance, and the tDELAY is the desired start-up delay. It is important that the time constant of the PWM soft start allows the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of Css:
C 20A = 5ms x --------------- = 100nF 0.95V
R
ChooseR BIAS = 214
SS
Bypass the FAN4800 locally with a 1.0 mF ceramic capacitor. In most applications, an electrolytic capacitor of between 47mF and 220mF is also required across the part , both for filtering and as a part of the start-up bootstrap circuitry.
Use caution when using this minimum soft start capacitance value because it can cause premature charging of the SS capacitor and activation of the PWM section if VFB is in the hysteresis band of the VIN OK comparator at start-up. The magnitude of VFB at start-up is related both to line voltage and nominal PFC output voltage. Typically, a 1.0mF soft-start capacitor will allow time for VFB and PFCOUT to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms.
Generating Vcc
After turning on the FAN4800 at 13V, the operating voltage can vary from 10V to 17.9V. The threshold voltage of the Vcc OVP comparator is 17.9V. and its hysteresis is 1.5V. When Vcc reaches 17.9V, PFC OUT will be low, and the PWM section will not be disturbed. There are two ways to generate Vcc. One way is to use auxiliary power supply around 15V, and the other way is to use bootstrap winding to self-bias the FAN4800 system. The bootstrap winding can be either taped from the PFC boost choke or from the transformer of the DC-to-DC stage. The ratio of the bootstrap's winding transformer for the bootstrap should be set between 18V and 15V. A filter network is recommended between Vcc(pin 13)and bootstrap winding. The resistor of the filter can be set as following.
R FILTER x I vcc 2V, I vcc =I op + ( Q PFCFET + Q PWMFET )
x fsw
Iop = 2.5mA ( typ. )
If anything goes wrong, and Vcc goes beyond 17.9V, the PFC gate(pin 12) drive goes low and the PWM gate drive (pin 11) remains working. The resistor's value must be chosen to meet the operating current requirement of the FAN4800 itself (5mA, max.) in addition to the current required by the two gate driver outputs.
14
FAN4800
Leading/Trailing Modulation
Conventional PWM techniques employ trailing edge modulation in which the switch turns on right after the trailing edge of the system clock. The error amplifier output is then compared with the modulating ramp up. The effective duty cycle of the trailing edge modulation is determined during the on-time of the switch. Figure 4 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned off exactly at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch is turned on. The effective duty-cycle of the leading edge modu-
lation is determined during off-time of the switch. Figure 5 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1(SW 1) turns off and switch 2(SW2) turns on at the same instant to minimize the momentary no-load period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC's output ripple voltage can be reduced by as much as 30% using the leading edge modulation method.
L1 I1 + V IN DC SW 1
SW 2
I2
I3
R AM P
I4 RL C1
V E AO
REF
EA
U3
VE A O CMP D FF R U1 D U2 Q C LK Q
T IM E
RAMP OSC C LK
U4
T IM E
Figure 4. Typical Trailing Edge Control Scheme
L1 I1 + VIN DC SW 1 C1 SW 2 I2 I3 I4 RL
RAM P
VE AO
U3
EA
VE A O CMP D FF R U1 D U2 Q C LK Q
TIM E
RE F RA M P O SC C LK
U4
TIM E
Figure 5. Typical Leading Edge Control Scheme
15
16
D2/1N5406 L1 VDC/+380V Q1 IRF840A + R21 22 D9 MBRS 140 T1B C12 + 10uF 35V L2 C24 1uF + C21 1800uF T2 D11B MBR2545CT R14 33 R4 15.4K C20 1uF R6 41.2K R10 6.2K C7/NOT USED R12 71.5K C6/1.5nF R9 1K 16 D4 MMBZ5245B Vcc REF R13 10K 15 14 13 12 11 10 9 C15 C16 C13 C14 10nF1uF 0.1uF1uF R11 845K C9 10nF C8 68nF R16 10K C10 10uF C23 100nF VFB T1A R19 220 U2 MOC8112 Q4 MMBT3904 R15 3 R20A 2.2 R20B 2.2 R23 1.5K RAMP2/DCILIM Q3 IRF820A D6 RGF1J R24 1.2K D7 MMBZ5245B D11A MBR2545CT R30 4.7K 12V 12V, 100W D5 RGF1J R28 240 C4 10nF C6 100uF C25 R7B 178K 0.1uF T2C R7A Q2G R17 178K 33 NOTE: Q2 IRF820A R27 75K R1A 453K + C26 330uF BR1 4A,600V KBL06 R2A 453K L1; PREMIER MAGNETICS TSD-1047 L2; PREMIER MAGNETICS VTP-05007 T1; PREMIER MAGNETICS PMGO-03 T2; PREMIER MAGNETICS TSO-735 D1 15L9R460P2 D3 RGF1J R2B 453K R3 110K R1B 453K R18 220 + C22 4.7uF FAN4800 1 IEAO IAC ISENSE VRMS SS VDC PWM OUT GND DC ILIMIT RAMP1 RAMP2 PFC OUT Vcc VREF VFB VEAO 2 3 4 5 6 7 8 C26 100nF R22 8.66K R26 10K C31 D8 1nF MBRS 140 R8 D10 2.37K MBRS 140 U3 TL431A C11 10nF VDC C17 220pF PRI GND R25 2.26K 12V RET 12V RETUR
FAN4800
F1 3.15A
C1 0.68uF
ISENSE
R5C R5A R5B 1.2 1.2 1.2
R5D 1.2
C3 0.1uF
Application Circuit (Current Mode)
C2 0.47uF
R31 100
RAMP1
D12 1N5401
C19 C18 1.0uF 470pF
D13 1N5401
D3 NOTE: VBUSS T2C R19 33 T1B D7 16V D13A T2 D13B R18 33 Q3 IRF820A D6 600V R29 1.2K R34 240 R30 1.5K C22 10uF C20 0.47uF C24 0.47uF C21 1500uF C26 0.47uF C28 1000uF L2 L3 R24 10K D5 600V 12V 12V 100W
F1 3.15A R27 82k R9 249k R14 383K R28 D2 240 15V 1N4744 C12 10uF 35V C27 47uF R20 22 C4 4.7nF C5 100uF C25 0.1uF Q1 IRF840A R13 383K Q2G Q2 IRF820A
L1
D1 8A FES16JT
BR1 4A,600V KBL06
C1 0.47uF
R1 357K
D7, D8, D9; 1N9668 D3, D5, D6; UF4005 D13; MBR2545CT L1; PREMIER MAGNETICS TSD-1047 L2; PREMIER MAGNETICS VTP-05007 L3; PREMIER MAGNETICS TSD-904 T1; PREMIER MAGNETICS PMGO-03 T2; PREMIER MAGNETICS TSO-735
R2 357K
R5 1.2
R6 1.2
R7 1.2 R10 249k
R8 1.2
C3 0.22uF
R3 100K
C2 0.47uF R38 42.2K R16 10K C7 150pF R12 68.1K C6 1.5nF R37 1K Q4 2N3904 16 15 14 13 12 11 10 9 D8 R15 4.99K R35 61.9k C11 220pF C17 470pF C18 220pF PRI GND C19 330pF D9 C14 1.0uF R11 412K C9 15nF C13 C8 0.22uF 150pF R26 10K VFB 1N4733A Vcc D4 5.1V R25 10K REF T1A FAN4800 1 IEAO IAC VFB VREF Vcc PFC OUT PWM OUT GND DC ILIMIT ISENSE VRMS SS VDC RAMP1 RAMP2 VEAO 2 3 4 5 6 7 8 R23 220 R17 3 R21 2.2 R22 2.2
Application Circuit (Voltage Mode)
R4 13.2K
R36 33
U2 MOC8112 R40 10K R32 8.66K
R39 470
R31 10K
RT/CT
J8 C10 10uF
C23 10nF
D10 1N4148
C15 C16 1.0uF 470pF
U3 TL431A
D11 1N4148
VDC
R33 2.26K 12V RET 12V RETURN
D12 1N4148
FAN4800
17
FAN4800
Mechanical Dimensions
Package
16-DIP
0.81 ) 0.032 #16 ( #1 6.40 0.20 0.252 0.008
19.80 MAX 0.780
19.40 0.20 0.764 0.008
#8
#9
7.62 0.300
3.25 0.20 0.128 0.008
0.38 0.014 MIN
5.08 MAX 0.200
3.30 0.30 0.130 0.012
0~15
0.25 -0.05 0.010 -0.002
+0.004
+0.10
18
2.54 0.100
0.46 0.10 0.018 0.004
1.50 0.10 0.059 0.004
FAN4800
Ordering Information
Product Number FAN4800IN Package 16-Pin PDIP Operating Temperature -40C ~ +125C
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 10/10/05 0.0m 001 Stock#DSxxxxxxxx 2005 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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